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functional block diagram ref out sha comp 20k 10k 5k 2.5k 2.5k 5k 12 12 AD1674 agnd bip off ref in 20v in 10v in idac 12 control ce 12/8 cs r/c a 0 5k 10k aa aa sar aa aa clock a a 10v ref a a a a a a registers / 3-state output buffers dac sts db11 (msb) db0 (lsb) rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 12-bit 100 ksps a/d converter AD1674* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features complete monolithic 12-bit 10 m s sampling adc on-board sample-and-hold amplifier industry standard pinout 8- and 16-bit microprocessor interface ac and dc specified and tested unipolar and bipolar inputs 6 5 v, 6 10 v, 0 vC10 v, 0 vC20 v input ranges commercial, industrial and military temperature range grades mil-std-883 and smd compliant versions available product description the AD1674 is a complete, multipurpose, 12-bit analog-to- digital converter, consisting of a user-transparent onboard sample-and-hold amplifier (sha), 10 volt reference, clock and three-state output buffers for microprocessor interface. the AD1674 is pin compatible with the industry standard ad574a and ad674a, but includes a sampling function while delivering a faster conversion rate. the on-chip sha has a wide input bandwidth supporting 12-bit accuracy over the full nyquist bandwidth of the converter. the AD1674 is fully specified for ac parameters (such as s/ (n+d) ratio, t hd, and imd) and dc parameters (offset, full-s cale error, etc.). with both ac and dc specifications, the AD1674 is ideal for use in signal processing and traditional dc measure- ment applications. the AD1674 design is implemented using analog devices bimos ii process allowing high performance bipolar analog cir- cuitry to be combined on the same die with digital cmos logic. five different temperature grades are available. the AD1674j and k grades are specified for operation over the 0 c to +70 c temperature range. the a and b grades are specified from C40 c to +85 c; the AD1674t grade is specified from C55 c to +125 c. the j and k grades are available in both 28-lead plastic dip and soic. the a and b grade devices are available in 28-lead hermetically sealed ceramic dip and 28-lead soic. the t grade is available in 28-lead hermetically sealed ceramic dip. * protected by u. s. patent nos. 4,962,325; 4,250,445; 4,808,908; re30586 . product highlights 1. industry standard pinout: the AD1674 utilizes the pinout established by the industry standard ad574a and ad674a. 2. integrated sha: the AD1674 has an integrated sha which supports the full nyquist bandwidth of the converter. the sha function is transparent to the user; no wait-states are needed for sha acquisition. 3. dc and ac specified: in addition to traditional dc specifica- tions, the AD1674 is also fully specified for frequency do- main ac parameters such as total harmonic distortion, signal-to-noise ratio and input bandwidth. these parameters can be tested and guaranteed as a result of the onboard sha. 4. analog operation: the precision, laser-trimmed scaling and bipolar offset resistors provide four calibrated ranges: 0 v to +10 v and 0 v to +20 v unipolar, C5 v to +5 v and C10 v to +10 v bipolar. the AD1674 operates on +5 v and 12 v or 15 v power supplies. 5. flexible digital interface: on-chip multiple-mode three-state output buffers and interface logic allow direct connection to most microprocessors.
AD1674Cspecifications dc specifications AD1674j AD1674k parameter min typ max min typ max unit resolution 12 12 bits integral nonlinearity (inl) 1 1/2 lsb differential nonlinearity (dnl) (no missing codes) 12 12 bits unipolar offset 1 @ +25 c 3 2 lsb bipolar offset 1 @ +25 c 6 4 lsb full-scale error 1, 2 @ +25 c (with fixed 50 w resistor from ref out to ref in) 0.1 0.25 0.1 0.25 % of fsr temperature range 0 +70 0 +70 c temperature drift 3 unipolar offset 2 2 1 lsb bipolar offset 2 2 1 lsb full-scale error 2 6 3 lsb power supply rejection v cc = 15 v 1.5 v or 12 v 0.6 v 2 1 lsb v logic = 5 v 0.5 v 1/2 1/2 lsb v ee = C15 v 1.5 v or C12 v 0.6 v 2 1 lsb analog input input ranges bipolar C5 +5 C5 +5 volts C10 +10 C10 +10 volts unipolar 0 +10 0 +10 volts 0 +20 0 +20 volts input impedance 10 volt span 357357 k w 20 volt span 6 10 14 6 10 14 k w power supplies operating voltages v logic +4.5 +5.5 +4.5 +5.5 volts v cc +11.4 +16.5 +11.4 +16.5 volts v ee C16.5 C11.4 C16.5 C11.4 volts operating current i logic 58 58 ma i cc 10 14 10 14 ma i ee 14 18 14 18 ma power dissipation 385 575 385 575 mw internal reference voltage 9.9 10.0 10.1 9.9 10.0 10.1 volts output current (available for external loads) 4 2.0 2.0 ma (external load should not change during conversion notes 1 adjustable to zero. 2 includes internal voltage reference error. 3 maximum change from 25 c value to the value at t min or t max . 4 reference should be buffered for 12 v operation. all min and max specifications are guaranteed. specifications subject to change without notice. rev. c C2C (t min to t max , v cc = +15 v 6 10% or +12 v 6 5%, v logic = +5 v 6 10%, v ee = C15 v 6 10% or C12 v 6 5% unless otherwise noted)
rev. c C3C AD1674 AD1674a AD1674b AD1674t parameter min typ max min typ max min typ max unit resolution 12 12 12 bits integral nonlinearity (inl) 1 1/2 1/2 lsb 1 1/2 1 lsb differential nonlinearity (dnl) (no missing codes) 12 12 12 bits unipolar offset 1 @ +25 c 2 2 2 lsb bipolar offset 1 @ +25 c 6 3 3 lsb full-scale error 1, 2 @ +25 c (with fixed 50 w resistor from ref out to ref in) 0.1 0.25 0.1 0.125 0.1 0.125 % of fsr temperature range C40 +85 C40 +85 C55 +125 c temperature drift 3 unipolar offset 2 2 1 1 lsb bipolar offset 2 2 1 2 lsb full-scale error 2 8 5 7 lsb power supply rejection v cc = 15 v 1.5 v or 12 v 0.6 v 2 1 1 lsb v logic = 5 v 0.5 v 1/2 1/2 1/2 lsb v ee = C15 v 1.5 v or C12 v 0.6 v 2 1 1 lsb analog input input ranges bipolar C5 +5 C5 +5 C5 +5 volts C10 +10 C10 +10 C10 +10 volts unipolar 0 +10 0 +10 0 +10 volts 0 +20 0 +20 0 +20 volts input impedance 10 volt span 357357357 k w 20 volt span 6 10 14 6 10 14 6 10 14 k w power supplies operating voltages v logic +4.5 +5.5 +4.5 +5.5 +4.5 +5.5 volts v cc +11.4 +16.5 +11.4 +16.5 +11.4 +16.5 volts v ee C16.5 C11.4 C16.5 C11.4 C16.5 C11.4 volts operating current i logic 58 58 58 ma i cc 10 14 10 14 10 14 ma i ee 14 18 14 18 14 18 ma power dissipation 385 575 385 575 385 575 mw internal reference voltage 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 volts output current (available for external loads) 4 2.0 2.0 2.0 ma (external load should not change during conversion
AD1674Cspecifications ac specifications AD1674j/a AD1674k/b/t parameter min typ max min typ max units signal to noise and distortion (s/n+d) ratio 2, 3 69 70 70 71 db total harmonic distortion (thd) 4 C90 C82 C90 C82 db 0.008 0.008 % peak spurious or peak harmonic component C92 C82 C92 C82 db full power bandwidth 1 1 mhz full linear bandwidth 500 500 khz intermodulation distortion (imd) 5 second order products C90 C80 C90 C80 db third order products C90 C80 C90 C80 db sha (specifications are included in overall timing specifications) aperture delay 50 50 ns aperture jitter 250 250 ps acquisition time 1 1 m s digital specifications parameter test conditions min max units logic inputs v ih high level input voltage +2.0 v logic +0.5 v v v il low level input voltage C0.5 +0.8 v i ih high level input current (v in = 5 v) v in = v logic C10 +10 m a i il low level input current (v in = 0 v) v in = 0 v C10 +10 m a c in input capacitance 10 pf logic outputs v oh high level output voltage i oh = 0.5 ma +2.4 v v ol low level output voltage i ol = 1.6 ma +0.4 v i oz high-z leakage current v in = 0 to v logic C10 +10 m a c oz high-z output capacitance 10 pf notes 1 f in amplitude = C0.5 db (9.44 v p-p) 10 v bipolar mode unless otherwise noted. all measurements referred to C0 db (9.997 v p-p) input signal unless otherwise noted. 2 specified at worst case temperatures and supplies after one minute warm-up. 3 see figures 12 and 13 for other input frequencies and amplitudes. 4 see figure 11. 5 fa = 9.08 khz, fb = 9.58 khz with f sample = 100 khz. see definition of specifications section and figure 15. all min and max specifications are guaranteed. specifications subject to change without notice. C4C rev. c (t min to t max , with v cc = +15 v 6 10% or +12 v 6 5%, v logic = +5 v 6 10%, v ee = C15 v 6 10% or C12 v 6 5%, f sample = 100 ksps, f in = 10 khz, stand-alone mode unless otherwise noted) 1 (for all grades t min to t max , with v cc = +15 v 6 10% or +12 v 6 5%, v logic = +5 v 6 10%, v ee = C15 v 6 10% or C12 v 6 5%)
AD1674 rev. c C5C (for all grades t min to t max with v cc = +15 v 6 10% or +12 v 6 5%, v logic = +5 v 6 10%, v ee = C15 v 6 10% or C12 v 6 5%; v il = 0.4 v, v ih = 2.4 v unless otherwise noted) switching specifications converter start timing (figure 1) j, k, a, b, grades t grade parameter symbol min typ max min typ max units conversion time 8-bit cycle t c 78 78 m s 12-bit cycle t c 910 910 m s sts delay from ce t dsc 200 225 ns ce pulse width t hec 50 50 ns cs to ce setup t ssc 50 50 ns cs low during ce high t hsc 50 50 ns r/ c to ce setup t src 50 50 ns r/ c low during ce high t hrc 50 50 ns a 0 to ce setup t sac 00ns a 0 valid during ce high t hac 50 50 ns read timingfull control mode (figure 2) j, k, a, b, grades t grade parameter symbol min typ max min typ max units access time t dd 1 75 150 75 150 ns data valid after ce low t hd 25 2 25 2 ns 20 3 15 4 ns output float delay t hl 5 150 150 ns cs to ce setup t ssr 50 50 ns r/ c to ce setup t srr 00ns a 0 to ce setup t sar 50 50 ns cs valid after ce low t hsr 00ns r/ c high after ce low t hrr 00ns a 0 valid after ce low t har 50 50 ns notes 1 t dd is measured with the load circuit of figure 3 and is defined as the time required for an output to cross 0.4 v or 2.4 v. 2 0 c to t max . 3 at C40 c. 4 at C55 c. 5 t hl is defined as the time required for the data lines to change 0.5 v when loaded with the circuit of figure 3. all min and max specifications are guaranteed. specifications subject to change without notice. test v cp c out access time high z to logic low 5 v 100 pf float time logic high to high z 0 v 10 pf access time high z to logic high 0 v 100 pf float time logic low to high z 5 v 10 pf t hec ce sts db11 ?db0 a 0 cs __ r/c _ t ssc t hsc t src t hrc t sac t hac t c t dsc high impedance figure 1. converter start timing high impedance ce sts db11 ?db0 a 0 cs __ r/c _ t hsr t ssr t hrr t sar t har t dd t hl high imp. data valid t hd t hs t ssr figure 2. read timing v cp d out c out i oh i ol figure 3. load circuit for bus timing specifications
AD1674 rev. c C6C ordering guide inl s/(n+d) package package model 1 temperature range (t min to t max )(t min to t max ) description option 2 AD1674jn 0 c to +70 c 1 lsb 69 db plastic dip n-28 AD1674kn 0 c to +70 c 1/2 lsb 70 db plastic dip n-28 AD1674jr 0 c to +70 c 1 lsb 69 db plastic soic r-28 AD1674kr 0 c to +70 c 1/2 lsb 70 db plastic soic r-28 AD1674ar C40 c to +85 c 1 lsb 69 db plastic soic r-28 AD1674br C40 c to +85 c 1/2 lsb 70 db plastic soic r-28 AD1674ad C40 c to +85 c 1 lsb 69 db ceramic dip d-28 AD1674bd C40 c to +85 c 1/2 lsb 70 db ceramic dip d-28 AD1674td C55 c to +125 c 1 lsb 70 db ceramic dip d-28 notes 1 for details on grade and package offerings screened in accordance with mil-std-883, refer to the analog devices military products databook or current AD1674/883b data sheet. smd is also available. 2 n = plastic dip; d = hermetic ceramic dip; r = plastic soic. timingstand-alone mode (figures 4a and 4b) j, k, a, b grades t grade parameter symbol min typ max min typ max units data access time t ddr 150 150 ns low r/ c pulse width t hrl 50 50 ns sts delay from r/ c t ds 200 225 ns data valid after r/ c low t hdr 25 25 ns sts delay after data valid t hs 0.6 0.8 1.2 0.6 0.8 1.2 m s high r/ c pulse width t hrh 150 150 ns note all min and max specifications are guaranteed. specifications subject to change without notice. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1674 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. data valid data valid high-z sts db11 ?db0 r/c _ t hrl t ds t c t hs t hdr figure 4a. stand-alone mode timing low pulse for r/ c data valid high-z high-z sts db11 ?db0 r/c _ t hrh t ds t c t ddr t hdr t hl figure 4b. stand-alone mode timing high pulse for r/ c absolute maximum ratings* v cc to digital common . . . . . . . . . . . . . . . . . . . 0 to + 16.5 v v ee to digital common . . . . . . . . . . . . . . . . . . . . . 0 to C16.5 v v logic to digital common . . . . . . . . . . . . . . . . . . 0 v to +7 v analog common to digital common . . . . . . . . . . . . . . . 1 v digital inputs to digital common . . . C0.5 v to v logic +0.5 v analog inputs to analog common . . . . . . . . . . . . v ee to v cc 20 v in to analog common . . . . . . . . . . . . . . . . . v ee to +24 v ref out . . . . . . . . . . . . . . . . . indefinite short to common . . . . . . . . . . . . . . . . . . . . . . . . . . . momentary short to v cc junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mw lead temperature, soldering (10 sec) . . . . . . . +300 c, 10 sec storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD1674 rev. c C7C pin description symbol pin no. type name and function agnd 9 p analog ground (common). a 0 4 di byte address/short cycle. if a conversion is started with a 0 active low, a full 12-bit conversion cycle is initiated. if a 0 is active high during a convert start, a shorter 8-bit conversion cycle results. during read (r/ c = 1) with 12/ 8 low, a 0 = low enables the 8 most significant bits (db4Cdb11), and a 0 = high enables db3Cdb0 and sets db7Cdb4 = 0. bip off 12 ai bipolar offset. connect t hrough a 50 w resistor to ref out for bipolar operation or to analog common for unipolar operation. ce 6 di chip enable. chip enable is active high and is used to initiate a convert or read operation. cs 3 di chip select. chip select is active low. db11Cdb8 27C24 do data bits 11 through 8. in the 12-bit format (see 12/ 8 and a 0 pins), these pins provide the up- per 4 bits of data. in the 8-bit format, they provide the upper 4 bits when a 0 is low and are disabled when a 0 is high. db7Cdb4 23C20 do data bits 7 through 4. in the 12-bit format these pins provide the middle 4 bits of data. in the 8-bit format they provide the middle 4 bits when ao is low and all zeroes when a 0 is high. db3Cdb0 19C16 do data bits 3 through 0. in the 12-bit format these pins provide the lower 4 bits of data. in the 8-bit format these pins provide the lower 4 bits of data when a 0 is high, they are disabled when a 0 is low. dgnd 15 p digital ground (common). ref out 8 ao +10 v reference output. r/ c 5 di read/convert. in the full control mode r/ c is active high for a read operation and active low for a convert operation. in the stand-alone mode, the falling edge of r/ c initiates a conversion. ref in 10 ai reference input is connected through a 50 w resistor to +10 v reference for normal operation. sts 28 do status is active high when a conversion is in progress and goes low when the conversion is completed. v cc 7 p +12 v/+15 v analog supply. v ee 11 p C12 v/C15 v analog supply. v logic 1 p +5 v logic supply. 10 v in 13 ai 10 v span input, 0 v to +10 v unipolar mode or C5 v to +5 v bipolar mode. when using the AD1674 in the 20 v span 10 v in should not be connected. 20 v in 14 ai 20 v span input, 0 v to +20 v unipolar mode or C10 v to +10 v bipolar mode. when using the AD1674 in the 10 v span 20 v in should not be connected. 12/ 8 2 di the 12/ 8 pin determines whether the digital output data is to be organized as two 8-bit words (12/ 8 low) or a single 12-bit word (12/ 8 high). type: ai = analog input ao = analog output di = digital input do = digital output p = power functional block diagram ref out sha comp 20k 10k 5k 2.5k 2.5k 5k 12 12 AD1674 agnd bip off ref in 20v in 10v in idac 12 control ce 12/8 cs r/c a 0 5k 10k aa aa sar aa aa clock aa aa 10v ref a a a a a a registers / 3-state output buffers dac sts db11 (msb) db0 (lsb) pin configuration top view (not to scale) AD1674 18 28 27 24 23 22 26 25 21 20 19 17 16 15 13 1 2 5 6 7 3 4 8 9 10 12 14 v logic ce v cc a 0 ref out agnd ref in v ee bip off 10v in 20v in cs 12/8 r/c sts db11(msb) db8 db7 db6 db10 db9 db5 db4 db3 db2 db1 db0(lsb) dgnd 11
AD1674 rev. c C8C definition of specifications integral nonlinearity (inl) the ideal transfer function for an adc is a straight line drawn between zero and full scale. the point used as zero occurs 1/2 lsb before the first code transition. full scale is defined as a level 1 1/2 lsb beyond the last code transition. integral nonlinearity is the worst-case deviation of a code from the straight line. the deviation of each code is measured from the middle of that code. differential nonlinearity (dnl) a specification which guarantees no missing codes requires that every code combination appear in a monotonic increasing sequence as the analog input level is increased. thus every code must have a finite width. the AD1674 guarantees no missing codes to 12-bit resolution; all 4096 codes are present over the entire operating range. unipolar offset the first transition should occur at a level 1/2 lsb above ana- log common. unipolar offset is defined as the deviation of the actual transition from that point at 25 c. this offset can be adjusted as shown in figure 11. bipolar offset in the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 lsb below analog common. the bipolar offset error specifies the deviation of the actual transition from that point at 25 c. this offset can be adjusted as shown in figure 12. full-scale error the last transition (from 1111 1111 1110 to 1111 1111 1111 ) should occur for an analog value 1 1/2 lsb below the nominal full scale (9.9963 volts for 10 volts full scale). the full-scale error is the deviation of the actual level of the last transition from the ideal level at 25 c. the full-scale error can be adjusted to zero as shown in figures 11 and 12. temperature drift the temperature drifts for full-scale error, unipolar offset and bipolar offset specify the maximum change from the initial (25 c) value to the value at t min or t max . power supply rejection the effect of power supply error on the performance of the device will be a small change in full scale. the specifications show the maximum full-scale change from the initial value with the supplies at various limits. frequency-domain testing the AD1674 is tested dynamically using a sine wave input and a 2048 point fast fourier transform (fft) to analyze the resulting output. coherent sampling is used, wherein the adc sampling frequency and the analog input frequency are related to each other by a ratio of integers. this ensures that an integral multiple of input cycles is captured, allowing direct fft pro- cessing without windowing or digital filtering which could mask some of the dynamic characteristics of the device. in addition, the frequencies are chosen to he relatively prime (no common factors) to maximize the number of different adc codes that are present in a sample sequence. the result, called prime coherent sampling, is a highly accurate and repeatable measure of the actual frequency-domain response of the converter. nyquist frequency an implication of the nyquist sampling theorem, the nyquist frequency of a converter is that input frequency which is one- half the sampling frequency of the converter. signal-to-noise and distortion (s/n+d) ratio s/(n+d) is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of a full-scale input signal and is ex- pressed as a percentage or in decibels. for input signals or harmonics that are above the nyquist frequency, the aliased component is used. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. . . . intermodulation terms are those for which m or n is not equal to zero. for example, the second order terms are (fa + fb) and (fa C fb) and the third order terms are (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the imd products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. the two signals are of equal amplitude and the peak value of their sums is C0.5 db from full scale. the imd products are normalized to a 0 db input signal. full-power bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 db for a full-scale input. full-linear bandwidth the full-linear bandwidth is the input frequency at which the slew rate limit of the sample-hold-amplifier (sha) is reached. at this point, the amplitude of the reconstructed fundamental has degraded by less than C0.1 db. beyond this frequency, dis- tortion of the sampled input signal increases significantly. aperture delay aperture delay is a measure of the shas performance and is measured from the falling edge of read/convert (r/ c ) to when the input signal is held for conversion. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d.
amplitude ?db input frequency ?khz 10000 ?00 ?20 10 1 ?0 ?0 ?0 ?0 0 1000 thd aaa 2 nd harmonic aaa aaa 3 rd harmonic aaaa aaaa f sample = 100ksps full-scale = +10v 100 figure 5. harmonic distortion vs. input frequency typical dynamic performanceCAD1674 general circuit operation the AD1674 is a complete 12-bit, 10 m s sampling analog-to- digital converter. a block diagram of the AD1674 is shown on page 7. when the control section is commanded to initiate a conversion (as described later), it places the sample-and-hold amplifier (sha) in the hold mode, enables the clock, and resets the suc- cessive approximation register (sar). once a conversion cycle has begun, it cannot be stopped or restarted and data is not available from the output buffers. the sar, timed by the inter- nal clock, will sequence through the conversion cycle and return an end-of-convert flag to the control section when the conver- sion has been completed. the control section will then disable the clock, switch the sha to sample mode, and delay the sts low going edge to allow for acquisition to 12-bit accuracy. the control section will allow data read functions by external command anytime during the sha acquisition interval. during the conversion cycle, the internal 12-bit, 1 ma full-scale current output dac is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb) to pro- vide an output that accurately balances the current through the 5 k w resistor from the input signal voltage held by the sha. the shas input scaling resistors divide the input voltage by 2 for the 10 v input span and by 4 v for the 20 v input span, maintaining a 1 ma full-scale output current through the 5 k w resistor for both ranges. the comparator determines whether the addition of each successively weighted bit current causes the dac current sum to be greater than or less than the input cur- rent. if the sum is less, the bit is left on; if more, the bit is turned off. after testing all the bits, the sar contains a 12-bit binary code which accurately represents the input signal to within 1/2 lsb. control logic the AD1674 may be operated in one of two modes, the full- control mode and the stand-alone mode. the full-control mode utilizes all the AD1674 control signals and is useful in systems that address decode multiple devices on a single data bus. the stand-alone mode is useful in systems with dedicated input ports available and thus not requiring full bus interface capability. table i is a truth table for the AD1674, and figure 10 illus- trates the internal logic circuitry. table i. AD1674a truth table ce cs r/ c 12/ 8 a 0 operation 0 x x x x none x 1 x x x none 1 0 0 x 0 initiate 12-bit conversion 1 0 0 x 1 initiate 8-bit conversion 1 0 1 1 x enable 12-bit parallel output 1 0 1 0 0 enable 8 most significant bits 1 0 1 0 1 enable 4 lsbs +4 trailing zeroes rev. c C9C figure 7. s/(n+d) vs. input amplitude 0 ?30 50 ?00 ?20 5 ?10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 45 35 30 15 10 frequency ?khz amplitude ?db 20 25 40 figure 9. imd plot for f in = 9.08 khz (fa), 9.58 khz (fb) 0 ?40 50 ?0 ?20 5 ?00 0 ?0 ?0 ?0 45 40 35 30 25 20 15 10 frequency ?khz amplitude ?db figure 8. nonaveraged 2048 point fft at 100 ksps, f in = 25.049 khz input frequency ?khz s/(n+d) ?db 80 0 10000 20 10 10 1 40 30 50 60 70 1000 0db input ?0db input ?0db input 100 figure 6. s/(n+d) vs. input frequency and amplitude
AD1674 rev. c C10C q r s read s r q qb value of a 0 at last convert command eoc 12 eoc 8 sar reset 1? delay-hold settling 1 m s delay-acquisition nybble a nybble b nybble c nybble b = 0 to output buffers ce a 0 12/8 r/c cs d q qb en d q en clk enable status hold/sample figure 10. equivalent internal logic circuitry full-control mode chip enable (ce), chip select ( cs ) and read/ convert (r/ c ) are used to control convert or read modes of operation. either ce or cs may be used to initiate a conversion. the state of r/ c when ce and cs are both asserted determines whether a data read (r/ c = 1) or a convert (r/ c = 0) is in progress. r/ c should be low before both ce and cs are asserted; if r/ c is high, a read operation will momentarily occur, possibly resulting in system bus contention. stand-alone mode the AD1674 can be used in a stand-alone mode, which is useful in systems with dedicated input ports available and thus not requiring full bus interface capability. stand-alone mode applications are generally able to issue conversion start com- mands more precisely than full-control mode. this improves ac performance by reducing the amount of control-induced aper- ture jitter. in stand-alone mode, the control interface for the AD1674 and ad674a are identical. ce and 12/ 8 are wired high, cs and a 0 are wired low, and conversion is controlled by r/ c . the three-state buffers are enabled when r/ c is high and a con- version starts when r/ c goes low. this gives rise to two pos- sible control signalsa high pulse or a low pulse. operation with a low pulse is shown in figure 4a. in this case, the outputs are forced into the high impedance state in response to the fall- ing edge of r/ c and return to valid logic levels after the conver- sion cycle is completed. the sts line goes high 200 ns after r/ c goes low and returns low 1 m s after data is valid. if conversion is initiated by a high pulse as shown in figure 4b, the data lines are enabled during the time when r/ c is high. the falling edge of r/ c starts the next conversion and the data lines return to three-state (and remain three-state) until the next high pulse of r/ c . conversion timing once a conversion is started, the sts line goes high. convert start commands will be ignored until the conversion cycle is complete. the output data buffers will be enabled a minimum of 0.6 m s prior to sts going low. the sts line will return low at the end of the conversion cycle. the register control inputs, a 0 and 12/ 8 , control conversion length and data format. if a conversion is started with a 0 low, a full 12-bit conversion cycle is initiated. if a 0 is high during a convert start, a shorter 8-bit conversion cycle results. during data read operations, a 0 determines whether the three- state buffers containing the 8 msbs of the conversion result (a 0 = 0) or the 4 lsbs (a 0 = 1) are enabled. the 12/ 8 pin deter- mines whether the output data is to be organized as two 8-bit words (12/ 8 tied low) or a single 12-bit word (12/ 8 tied high). in the 8-bit mode, the byte addressed when a 0 is high contains the 4 lsbs from the conversion followed by four trail- ing zeroes. this organization allows the data lines to be over- lapped for direct interface to 8-bit buses without the need for external three-state buffers. input connections and calibration the 10 v p-p and 20 v p-p full-scale input ranges of the AD1674 accept the majority of signal voltages without the need for external voltage divider networks which could deteriorate the accuracy of the adc. the AD1674 is factory trimmed to minimize offset, linearity, and full-scale errors. in many applications, no calibration trim- ming will be required and the AD1674 will exhibit the accuracy limits listed in the specification tables. in some applications, offset and full-scale errors need to be trimmed out completely. the following sections describe the correct procedure for these various situations. unipolar range inputs figure 11 illustrates the external connections for the AD1674 in unipolar-input mode. the first output-code transition (from 0000 0000 0000 to 0000 0000 0001) should nominally occur for an input level of +1/2 lsb (1.22 mv above ground for a 10 v range; 2.44 mv for a 20 v range). to trim unipolar offset to this nominal value, apply a +1/2 lsb signal between pin 13 and ground (10 v range) or pin 14 and ground (20 v range) and ad- just r1 until the first transition is located. if the offset trim is not required, pin 12 can be connected directly to pin 9; the two resistors and trimmer for pin 12 are then not needed.
AD1674 rev. c C11C 100k AD1674 r1 100k ?5v +15v r2 100 w 100 w analog inputs 0 to +20v 0 to +10v 2 12/8 3 cs 4 a 0 5 r/c 6 ce 10 ref in 8 ref out 12 bip off 13 10v in 14 20v in 9 ana com sts 28 high bits 24-27 middle bits 20-23 low bits 16-19 +5v 1 +15v 7 ?5v 11 dig com 15 figure 11. unipolar input connections with gain and offset trims the full-scale trim is done by applying a signal 1 1/2 lsb below the nominal full scale (9.9963 v for a 10 v range) and adjusting r2 until the last transition is located (1111 1111 1110 to 1111 1111 1111). if full-scale adjustment is not required, r2 should be replaced with a fixed 50 w 1% metal film resistor. if ref out is connected directly to ref in, the additional full-scale error will be approximately 1%. bipolar range inputs the connections for the bipolar-input mode are shown in figure 12. either or both of the trimming potentiometers can be replaced with 50 w 1% fixed resistors if the specified AD1674 accuracy limits are sufficient for the application. if the pins are shorted together, the additional offset and gain errors will be approximately 1%. to trim bipolar offset to its nominal value, apply a signal 1/2 lsb below midrange (C1.22 mv for a 5 v range) and adjust r1 until the major carry transition is located (0111 1111 1111 to 1000 0000 0000). to trim the full-scale error, apply a signal 1 1/2 lsb below full scale (+4.9963 v for a 5 v range) and adjust r2 to give the last positive transition (1111 1111 1110 to 1111 1111 1111). these trims are interactive so several itera- tions may be necessary for convergence. a single-pass calibration can be done by substituting a negative full-scale trim for the bipolar offset trim (error at midscale), using the same circuit. first, apply a signal 1/2 lsb above minus full scale (C4.9988 v for a 5 v range) and adjust r1 until the minus full-scale transition is located (0000 0000 0001 to 0000 0000 0000). then perform the gain error trim as outlined above. r1 100 w ?0v ?v AD1674 r2 100 w analog inputs 2 12/8 3 cs 4 a 0 5 r/c 6 ce 10 ref in 8 ref out 12 bip off 13 10v in 14 20v in 9 ana com sts 28 high bits 24-27 middle bits 20-23 low bits 16-19 +5v 1 +15v 7 ?5v 11 dig com 15 figure 12. bipolar input connections with gain and offset trims reference decoupling it is recommended that a 10 m f tantalum capacitor be con- nected between ref in (pin 10) and ground. this has the effect of improving the s/(n+d) ratio through filtering possible broad-band noise contributions from the voltage reference. board layout designing with high resolution data converters requires careful attention to board layout. trace impedance is a significant issue. at the 12-bit level, a 5 ma current through a 0.5 w trace will develop a voltage drop of 2.5 mv, which is 1 lsb for a 10 v full-scale range. in addition to ground drops, inductive and ca- pacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital sig- nals. finally, power supplies should be decoupled in order to filter out ac noise. the AD1674 has a wide bandwidth sampling front end. this means that the AD1674 will see high frequency noise at the input, which nonsampling (or limited-bandwidth sampling) adcs would ignore. therefore, its important to make an effort to eliminate such high frequency noise through decoupling or by using an anti-aliasing filter at the analog input of the AD1674. analog and digital signals should not share a common path. each signal should have an appropriate analog or digital return routed close to it. using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. wide pc tracks, large gauge wire, and ground planes are highly recom- mended to provide low impedance signal paths. separate analog and digital ground planes are also desirable, with a single inter- connection point to minimize ground loops. analog signals should be routed as far as possible from digital signals and should cross them (if necessary) only at right angles. the AD1674 incorporates several features to help the users lay- out. analog pins are adjacent to help isolate analog from digital signals. ground currents have been minimized by careful circuit architecture. current through agnd is 2.2 ma, with little code-dependent variation. the current through dgnd is domi- nated by the return current for db11Cdb0. supply decoupling the AD1674 power supplies should be well filtered, well regu- lated, and free from high frequency noise. switching power sup- plies are not recommended due to their tendency to generate spikes which can induce noise in the analog system. decoupling capacitors should be used in very close layout prox- imity between all power supply pins and ground. a 10 m f tanta- lum capacitor in parallel with a 0.1 m f disc ceramic capacitor provides adequate decoupling over a wide range of frequencies. an effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. the circuit layout should attempt to locate the AD1674, associated analog input circuitry, and interconnec- tions as far as possible from logic circuitry. a solid analog ground plane around the AD1674 will isolate large switching ground currents. for these reasons, the use of wire-wrap circuit construction is not recommended; careful printed-circuit con- struction is preferred.
AD1674 rev. c C12C c1425bC10C3/94 printed in u.s.a. grounding if a single AD1674 is used with separate analog and digital ground planes, connect the analog ground plane to agnd and the digital ground plane to dgnd keeping lead lengths as short as possible. then connect agnd and dgnd together at the AD1674. if multiple AD1674s are used or the AD1674 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. this prevents large ground loops which inductively couple noise and allow digital currents to flow through the ana- log system. general microprocessor interface considerations a typical a/d converter interface routine involves several opera- tions. first, a write to the adc address initiates a conversion. the processor must then wait for the conversion cycle to com- plete, since most adcs take longer than one instruction cycle to complete a conversion. valid data can, of course, only be read after the conversion is complete. the AD1674 provides an out- put signal (sts) which indicates when a conversion is in progress. this signal can be polled by the processor by reading it through an external three-state buffer (or other input port). the sts signal can also be used to generate an interrupt upon completion of a conversion, if the system timing requirements are critical (bear in mind that the maximum conversion time of the AD1674 is only 10 microseconds) and the processor has other tasks to perform during the adc conversion cycle. an- other possible time-out method is to assume that the adc will take 10 microseconds to convert, and insert a sufficient number of no-op instructions to ensure that 10 microseconds of pro- cessor time is consumed. once it is established that the conversion is finished, the data can be read. in the case of an adc of 8-bit resolution (or less), a single data read operation is sufficient. in the case of convert- ers with more data bits than are available on the bus, a choice of data formats is required, and multiple read operations are needed. the AD1674 includes internal logic to permit direct in- terface to 8-bit or 16-bit data buses, selected by the 12/ 8 input. in 16-bit bus applications (12/ 8 high) the data lines (db11 through db0) may be connected to either the 12 most signifi- cant or 12 least significant hits of the data bus. the remaining four bits should be masked in software. the interface to an 8-bit data bus (12/ 8 low) contains the 8 msbs (db11 through db4). the odd address (a 0 high) contains the 4 lsbs (db3 through db0) in the upper half of the byte, followed by four trailing zeroes, thus eliminating bit masking instructions. AD1674 data format for 8-bit bus package information dimensions shown in inches and (mm). 28-pin ceramic dip package (d-28) 0.050 ?.010 (1.27 ?.254) seating plane 1.42 (36.07) 1.40 (35.56) 0.047 ?.007 (1.19 ?.178) 0.1 (2.54) 0.017 ?.003 (0.43 ?.076) 0.145 ?.02 (3.68 ?.51) 0.125 (3.17) min 0.6 (15.24) 0.010 ?.002 (0.254 ?.05) 0.095 (2.41) 0.085 (2.16) 0.59 ?.01 (14.98 ?.254) 14 15 pin 1 1 28 0.505 (12.83) 28-lead plastic dip package (n-28) pin 1 0.550 (13.97) 0.530 (13.462) 1 14 15 28 seating plane 1.450 (38.83) 1.440 (35.576) 0.200 (5.080) max 0.020 (0.508) 0.015 (0.381) 0.160 (4.06) 0.140 (3.56) 0.175 (4.45) 0.120 (3.05) 0.105 (2.67) 0.095 (2.41) 0.065 (1.65) 0.045 (1.14) 0.606 (15.39) 0.594 (15.09) 0.012 (0.305) 0.008 (0.203) 15 0 28-lead wide-body so package (r-28) pin 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 28 15 14 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.1043 (2.65) 0.0926 (2.35) 0.7125 (18.10) 0.6969 (17.70) 0.0118 (0.30) 0.0040 (0.10)

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